Bottom electrode contact for a vertical three-dimensional memory

ABSTRACT

Systems, methods and apparatus are provided for an array of vertically stacked memory cells having a bottom electrode contact for an array of vertically stacked memory cells. The bottom electrode contact is formed in a periphery region. The bottom electrode contact is electrically coupled to a number of bottom electrodes of capacitors that are also formed in the periphery region.

TECHNICAL FIELD

The present disclosure relates generally to semiconductor devices, andmore particularly, to a bottom electrode contact for verticalthree-dimensional (3D) memory.

BACKGROUND

Memory is often implemented in electronic systems, such as computers,cell phones, hand-held devices, etc. There are many different types ofmemory, including volatile and non-volatile memory. Volatile memory mayrequire power to maintain its data and may include random-access memory(RAM), dynamic random-access memory (DRAM), static random-access memory(SRAM), and synchronous dynamic random-access memory (SDRAM).Non-volatile memory may provide persistent data by retaining stored datawhen not powered and may include NAND flash memory, NOR flash memory,nitride read only memory (NROM), phase-change memory, e.g., phase-changerandom access memory, resistive memory, e.g., resistive random-accessmemory, cross-point memory, ferroelectric random-access memory (FeRAM),or the like.

Various memory devices include an array of memory cells that can eachinclude a storage node, such as a capacitor, and an access device, suchas a transistor. Peripheral circuitry such as driver circuitry,decoders, sense amplifiers, etc. can be used to access the memory cellsin association with reading and/or writing data. The peripheral regionoften includes various capacitors, which may be referred to as peripherycapacitors, that can be used to provide increased, e.g., boosted,voltages via capacitive coupling and/or can be used as filters to reduceor eliminate unwanted noise between various electrical nodes within thearray and/or periphery region, for example.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a schematic illustration of a vertical three-dimensional (3D)memory in accordance a number of embodiments of the present disclosure.

FIG. 2 is a perspective view illustrating a portion of a digit line forsemiconductor devices in accordance with a number of embodiments of thepresent disclosure.

FIG. 3 is a perspective view illustrating a portion of a digit line forsemiconductor devices in accordance with a number of embodiments of thepresent disclosure.

FIG. 4A-4K is a cross-sectional view for forming arrays of verticallystacked memory cells, at multiple stages of a semiconductor fabricationprocess in accordance with a number of embodiments of the presentdisclosure.

FIGS. 5A-5B illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells in accordance with a number of embodiments of thepresent disclosure.

FIGS. 6A to 6E illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells in accordance with a number of embodiments of thepresent disclosure.

FIGS. 7A to 7F illustrate an example method, at another stage of asemiconductor fabrication process, for forming arrays of verticallystacked memory cells in accordance with a number of embodiments of thepresent disclosure.

FIGS. 8A to 8N illustrate an example method, at another stage of asemiconductor fabrication process, for forming a bottom electrodecontact, in a periphery region, for an array of vertically stackedmemory cells, in accordance with a number of embodiments of the presentdisclosure.

FIG. 9 is a block diagram of an apparatus in the form of a computingsystem including a semiconductor device in accordance with a number ofembodiments of the present disclosure.

DETAILED DESCRIPTION

Embodiments of the present disclosure describe integrating formation ofcapacitors in a periphery region, e.g., “periphery capacitors,” withformation of capacitors in an array region, e.g., “array capacitors” or“cell capacitors,” within memory devices comprising arrays of verticallystacked memory cells, e.g., vertical 3D DRAM devices. As describedfurther herein, the periphery capacitors can comprise a common bottomelectrode contact. The periphery capacitors, which are formed in aperiphery region, can be coupled together in various manners via backend of line (BEOL) processing to provide the desired capacitances forarray operation. Integrating the periphery region capacitor formationwith the array region capacitor formation can provide various benefitssuch as improved, e.g., reduced, processing time associated with formingthe periphery capacitors via a formation process separate from the arrayformation process. The periphery capacitors can be utilized to storecharge used to, for example, activate word lines, boost voltages viacapacitive coupling, and/or can serve as high frequency filters toreduce/eliminate unwanted noise.

The figures herein follow a numbering convention in which the firstdigit or digits correspond to the figure number of the drawing and theremaining digits identify an element or component in the drawing.Similar elements or components between different figures may beidentified by the use of similar digits. For example, reference numeral111 may reference element “11” in FIG. 1 , and a similar element may bereferenced as 211 in FIG. 2 . Multiple analogous elements within onefigure may be referenced with a reference numeral followed by a hyphenand another numeral or a letter. For example, 103-1 may referenceelement 103-1 in FIG. 1 and 103-2 may reference element 103-2, which maybe analogous to element 103-1. Such analogous elements may be generallyreferenced without the hyphen and extra numeral or letter. For example,elements 103-1 and 103-2 or other analogous elements may be generallyreferenced as 103. As will be appreciated, elements shown in the variousembodiments herein can be added, exchanged, and/or eliminated so as toprovide a number of additional embodiments of the present disclosure. Inaddition, as will be appreciated, the proportion and the relative scaleof the elements provided in the figures are intended to illustrate theembodiments of the present disclosure and should not be taken in alimiting sense.

FIG. 1 is a block diagram of an apparatus in accordance a number ofembodiments of the present disclosure. FIG. 1 illustrates a circuitdiagram showing a cell array of a three dimensional (3D) semiconductordevice according to embodiments of the present disclosure. FIG. 1illustrates a cell array may have a plurality of sub cell arrays 101-1,101-2, . . . , 101-N. The sub cell arrays 101-1, 101-2, . . . , 101-Nmay be arranged along a second direction (D2) 105. Each of the sub cellarrays, e.g., sub cell array 101-2, may include a plurality of accesslines 103-1, 103-2, . . . , 103-Q (which also may be referred to awordlines). Also, each of the sub cell arrays, e.g., sub cell array101-2, may include a plurality of digit lines 107-1, 107-2, . . . ,107-P (which also may be referred to as bitlines, data lines, or senselines). In FIG. 1 , the digit lines 107-1, 107-2, . . . , 107-P areillustrated extending in a first direction (D1) 109 and the access lines103-1, 103-2, . . . , 103-Q are illustrated extending in a thirddirection (D3) 111. According to embodiments, the first direction (D1)109 and the second direction (D2) 105 may be considered in a horizontal(“X-Y”) plane. The third direction (D3) 111 may be considered in avertical (“Z”) plane. Hence, according to embodiments described herein,the access lines 103-1, 103-2, . . . , 103-Q are extending in a verticaldirection, e.g., third direction (D3) 111.

A memory cell, e.g., 110, may include an access device, e.g., accesstransistor, and a storage node located at an intersection of each accessline 103-1, 103-2, . . . , 103-Q and each digit line 107-1, 107-2, . . ., 107-P. Memory cells may be written to, or read from, using the accesslines 103-1, 103-2, . . . , 103-Q and digit lines 107-1, 107-2, . . . ,107-P. The digit lines 107-1, 107-2, . . . , 107-P may conductivelyinterconnect memory cells along horizontal columns of each sub cellarray 101-1, 101-2, . . . , 101-N, and the access lines 103-1, 103-2, .. . , 103-Q may conductively interconnect memory cells along verticalrows of each sub cell array 101-1, 101-2, . . . , 101-N. One memorycell, e.g. 110, may be located between one access line, e.g., 103-2, andone digit line, e.g., 107-2. Each memory cell may be uniquely addressedthrough a combination of an access line 103-1, 103-2, . . . , 103-Q anda digit line 107-1, 107-2, . . . , 107-P.

The digit lines 107-1, 107-2, . . . , 107-P may be or include conductingpatterns, e.g., metal lines, disposed on and spaced apart from asubstrate. The digit lines 107-1, 107-2, . . . , 107-P may extend in afirst direction (D1) 109. The digit lines 107-1, 107-2, . . . , 107-P inone sub cell array, e.g., 101-2, may be spaced apart from each other ina vertical direction, e.g., in a third direction (D3) 111.

The access lines 103-1, 103-2, . . . , 103-Q may be or includeconductive patterns, e.g., metal lines, extending in a verticaldirection with respect to the substrate, e.g., in a third direction (D3)111. The access lines in one sub cell array, e.g., 101-2, may be spacedapart from each other in the first direction (D1) 109.

A gate of a memory cell, e.g., memory cell 110, may be connected to anaccess line, e.g., 103-2, and a first conductive node, e.g., firstsource/drain region, of an access device, e.g., transistor, of thememory cell 110 may be connected to a digit line, e.g., 107-2. Each ofthe memory cells, e.g., memory cell 110, may be connected to a storagenode, e.g., capacitor. A second conductive node, e.g., secondsource/drain region, of the access device, e.g., transistor, of thememory cell 110 may be connected to the storage node, e.g., capacitor.While first and second source/drain region reference are used herein todenote two separate and distinct source/drain regions, it is notintended that the source/drain region referred to as the “first” and/or“second” source/drain regions have some unique meaning. It is intendedonly that one of the source/drain regions is connected to a digit line,e.g., 107-2, and the other may be connected to a storage node.

FIG. 2 illustrates a perspective view showing a three dimensional (3D)semiconductor device, e.g., a portion of a sub cell array 101-2 shown inFIG. 1 as a vertically oriented stack of memory cells in an array,according to some embodiments of the present disclosure. FIG. 3illustrates a perspective view showing unit cell, e.g., memory cell 110shown in FIG. 1 , of the 3D semiconductor device shown in FIG. 2 .

As shown in FIG. 2 , a substrate 200 may have formed thereon one of theplurality of sub cell arrays, e.g., 101-2, described in connection withFIG. 1 . For example, the substrate 200 may be or include a siliconsubstrate, a germanium substrate, or a silicon-germanium substrate, etc.Embodiments, however, are not limited to these examples.

As shown in the example embodiment of FIG. 2 , the substrate 200 mayhave fabricated thereon a vertically oriented stack of memory cells,e.g., memory cell 110 in FIG. 1 , extending in a vertical direction,e.g., third direction (D3) 211. According to some embodiments thevertically oriented stack of memory cells may be fabricated such thateach memory cell, e.g., memory cell 110 in FIG. 1 , is formed onplurality of vertical levels, e.g., a first level (L1), a second level(L2), and a third level (L3). The repeating, vertical levels, L1, L2,and L3, may be arranged, e.g., “stacked”, a vertical direction 211,e.g., third direction (D3) 111 shown in FIG. 1 , and may be separatedfrom the substrate 200 by an insulator material 220. Each of therepeating, vertical levels, L1, L2, and L3 may include a plurality ofdiscrete components, e.g., regions, to the laterally oriented accessdevices 230, e.g., transistors, and storage nodes, e.g., capacitors,including access line 203-1, 203-2, . . . , 203-Q connections and digitline 207-1, 207-2, . . . , 207-P connections. The plurality of discretecomponents to the laterally oriented access devices 230, e.g.,transistors, may be formed in a plurality of iterations of vertically,repeating layers within each level, as described in more detail below inconnection with FIGS. 4A-4K, and may extend horizontally in the seconddirection (D2) 205, analogous to second direction (D2) 105 shown in FIG.1 .

The plurality of discrete components to the laterally oriented accessdevices 230, e.g., transistors, may include a first source/drain region221 and a second source/drain region 223 separated by a channel region225, extending laterally in the second direction (D2) 205, and formed ina body of the access devices. In some embodiments, the channel region225 may include a channel material, such as silicon, germanium,silicon-germanium, and/or indium gallium zinc oxide (IGZO). In someembodiments, the first and the second source/drain regions, 221 and 223,can include an n-type dopant region formed in a p-type doped body to theaccess device to form an n-type conductivity transistor. In someembodiments, the first and the second source/drain regions, 221 and 223,may include a p-type dopant formed within an n-type doped body to theaccess device to form a p-type conductivity transistor. By way ofexample, and not by way of limitation, the n-type dopant may includephosphorous (P) atoms and the p-type dopant may boron (B) atoms formedin an oppositely doped body region of polysilicon semiconductormaterial. Embodiments, however, are not limited to these examples.

The storage node 227, e.g., capacitor, may be connected to onerespective end of the access device. As shown in FIG. 2 , the storagenode 227, e.g., capacitor may be connected to the second source/drainregion 223 of the access device. The storage node may be or includememory elements capable of storing data. Each of the storage nodes maybe a memory element using one of a capacitor, a magnetic tunnel junctionpattern, and/or a variable resistance body which includes a phase changematerial, etc. A number of embodiments provide that the storage node isa metal-insulator-metal (MIM) capacitor or a metal-ferroelectric-metal(MFM). Embodiments, however, are not limited to these examples. In someembodiments, the storage node associated with each access device of aunit cell, e.g., memory cell 110 in FIG. 1 , may similarly extend in thesecond direction (D2) 205, analogous to second direction (D2) 105 shownin FIG. 1 .

As shown in FIG. 2 , a plurality of horizontally oriented digit lines207-1, 207-2, . . . , 207-P extend in the first direction (D1) 209,analogous to the first direction (D1) 109 in FIG. 1 . However,embodiments are not so limited, for instance for a number ofembodiments, the digit lines, 207-1, 207-2, . . . , 207-P may extend ina vertical direction with respect to the substrate 200, e.g. indirection (D3) 211. The plurality of horizontally oriented digit lines207-1, 207-2, . . . , 207-P may be analogous to the digit lines 107-1,107-2, . . . , 107-P shown in FIG. 1 . The plurality of horizontallyoriented digit lines 207-1, 207-2, . . . , 207-P may be arranged, e.g.,“stacked”, along the third direction (D3) 211. The plurality ofhorizontally oriented digit lines 207-1, 207-2, . . . , 207-P mayinclude a conductive material. For example, the conductive material mayinclude one or more of a doped semiconductor, e.g., doped silicon, dopedgermanium, etc., a conductive metal nitride, e.g., titanium nitride,tantalum nitride, etc., a metal, e.g., tungsten (W), titanium (Ti),tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.,and/or a metal-semiconductor compound, e.g., tungsten silicide, cobaltsilicide, titanium silicide, etc. Embodiments, however, are not limitedto these examples.

Among each of the vertical levels, (L1) 213-1, (L2) 213-2, and (L3)213-P, the horizontally oriented memory cells, e.g., memory cell 110 inFIG. 1 , may be spaced apart from one another horizontally in the firstdirection (D1) 209. However, as described in more detail below inconnection with FIG. 4 et. Seq., the plurality of discrete components tothe laterally oriented access devices 230, e.g., first source/drainregion 221 and second source/drain region 223 separated by a channelregion 225, extending laterally in the second direction (D2) 205, andthe plurality of horizontally oriented digit lines 207-1, 207-2, . . . ,207-P extending laterally in the first direction (D1) 209, may be formedwithin different vertical layers within each level. For example, theplurality of horizontally oriented digit lines 207-1, 207-2, . . . ,207-P, extending in the first direction (D1) 209, may be disposed on,and in electrical contact with, top surfaces of first source/drainregions 221 and orthogonal to laterally oriented access devices 230,e.g., transistors, extending in laterally in the second direction (D2)205. In some embodiments, the plurality of horizontally oriented digitlines 207-1, 207-2, . . . , 207-P, extending in the first direction (D1)209 are formed in a higher vertical layer, farther from the substrate200, within a level, e.g., within level (L1), than a layer in which thediscrete components, e.g., first source/drain region 221 and secondsource/drain region 223 separated by a channel region 225, of thelaterally oriented access device are formed. In some embodiments, theplurality of horizontally oriented digit lines 207-1, 207-2, . . . ,207-P, extending in the first direction (D1) 209, may be connected tothe top surfaces of the first source/drain regions 221 directly and/orthrough additional contacts including metal silicides.

As shown in the example embodiment of FIG. 2 , the access lines, 203-1,203-2, . . . , 203-Q, extend in a vertical direction with respect to thesubstrate 200, e.g., in a third direction (D3) 211. However, embodimentsare not so limited, for instance for a number of embodiments, the accesslines, 203-1, 203-2, . . . , 203-Q may extend in a horizontal directionwith respect to the substrate 200, e.g. in direction (D1) 209 and/or(D2) 205. Further, as shown in FIG. 2 , the access lines, 203-1, 203-2,. . . , 203-Q, in one sub cell array, e.g., sub cell array 101-2 in FIG.1 , may be spaced apart from each other in the first direction (D1) 209.The access lines, 203-1, 203-2, . . . , 203-Q, may be provided,extending vertically relative to the substrate 200 in the thirddirection (D3) 211 between a pair of the laterally oriented accessdevices 230, e.g., transistors, extending laterally in the seconddirection (D2) 205, but adjacent to each other on a level, e.g., firstlevel (L1), in the first direction (D1) 209. Each of the access lines,203-1, 203-2, . . . , 203-Q, may vertically extend, in the thirddirection (D3), on sidewalls of respective ones of the plurality oflaterally oriented access devices 230, e.g., transistors, that arevertically stacked.

For example, and as shown in more detail in FIG. 3 , a first one of thevertically extending access lines, e.g., 203-1, may be adjacent asidewall of a channel region 225 to a first one of the laterallyoriented access devices 230, e.g., transistors, in the first level (L1)213-1, a sidewall of a channel region 225 of a first one of thelaterally oriented access devices 230, e.g., transistors, in the secondlevel (L2) 213-2, and a sidewall of a channel region 225 a first one ofthe laterally oriented access devices 230, e.g., transistors, in thethird level (L3) 213-P, etc. Similarly, a second one of the verticallyextending access lines, e.g., 203-2, may be adjacent a sidewall to achannel region 225 of a second one of the laterally oriented accessdevices 230, e.g., transistors, in the first level (L1) 213-1, spacedapart from the first one of laterally oriented access devices 230, e.g.,transistors, in the first level (L1) 213-1 in the first direction (D1)209. And the second one of the vertically extending access lines, e.g.,203-2, may be adjacent a sidewall of a channel region 225 of a secondone of the laterally oriented access devices 230, e.g., transistors, inthe second level (L2) 213-2, and a sidewall of a channel region 225 of asecond one of the laterally oriented access devices 230, e.g.,transistors, in the third level (L3) 213-P, etc. Embodiments are notlimited to a particular number of levels.

The vertically extending access lines, 203-1, 203-2, . . . , 203-Q, mayinclude a conductive material, such as, for example, one of a dopedsemiconductor material, a conductive metal nitride, metal, and/or ametal-semiconductor compound. The access lines, 203-1, 203-2, . . . ,203-Q, may correspond to wordlines (WL) described in connection withFIG. 1 .

As shown in the example embodiment of FIG. 2 , a conductive body contact295 may be formed extending in the first direction (D1) 209 along an endsurface of the laterally oriented access devices 230, e.g., transistors,in each level (L1) 213-1, (L2) 213-2, and (L3) 213-P above the substrate200. The body contact 295 may be connected to a body (326 as shown inFIG. 3 ), e.g., body region, of the laterally oriented access devices230, e.g., transistors, in each memory cell, e.g., memory cell 110 inFIG. 1 . The body contact 295 may include a conductive material such as,for example, one of a doped semiconductor material, a conductive metalnitride, metal, and/or a metal-semiconductor compound.

Although not shown in FIG. 2 , an insulating material may fill otherspaces in the vertically stacked array of memory cells. For example, theinsulating material may include one or more of a silicon oxide material,a silicon nitride material, and/or a silicon oxynitride material, etc.Embodiments, however, are not limited to these examples.

FIG. 3 illustrates in more detail a unit cell, e.g., memory cell 110 inFIG. 1 , of the vertically stacked array of memory cells, e.g., within asub cell array 101-2 in FIG. 1 , according to some embodiments of thepresent disclosure. As shown in FIG. 3 , the first and the secondsource/drain regions, 321 and 323, may be impurity doped regions to thelaterally oriented access devices 330, e.g., transistors. The first andthe second source/drain regions 321 and 323, may be analogous to thefirst and the second source/drain regions 221 and 223 shown in FIG. 2 .The first and the second source/drain regions may be separated by achannel 325 formed in a body of semiconductor material, e.g., bodyregion 326, of the laterally oriented access devices 330, e.g.,transistors. The first and the second source/drain regions, 321 and 323,may be formed from an n-type or p-type dopant doped in the body region326. Embodiments are not so limited.

For example, for an n-type conductivity transistor construction the bodyregion 326 of the laterally oriented access devices 330, e.g.,transistors, may be formed of a low doped (p−) p-type semiconductormaterial. In one embodiment, the body region 326 and the channel 325separating the first and the second source/drain regions, 321 and 323,may include a low doped, p-type, e.g., low dopant concentration (p−)polysilicon material consisting of boron (B) atoms as an impurity dopantto the polycrystalline silicon. The first and the second source/drainregions, 321 and 323, may also comprise a metal, and/or metal compositematerials containing ruthenium (Ru), molybdenum (Mo), nickel (Ni),titanium (Ti), copper (Cu), a highly doped degenerate semiconductormaterial, and/or at least one of indium oxide (In₂O₃), or indium tinoxide (In_(2-x)Sn_(x)O₃), formed using an atomic layer depositionprocess, etc. Embodiments, however, are not limited to these examples.As used herein, a degenerate semiconductor material is intended to meana semiconductor material, such as polysilicon, containing a high levelof doping with significant interaction between dopants, e.g.,phosphorous (P), boron (B), etc. Non-degenerate semiconductors, bycontrast, contain moderate levels of doping, where the dopant atoms arewell separated from each other in the semiconductor host lattice withnegligible interaction.

In this example, the first and the second source/drain regions, 321 and321, may include a high dopant concentration, n-type conductivityimpurity, e.g., high dopant (n+) doped in the first and the secondsource/drain regions, 321 and 323. In some embodiments, the high dopant,n-type conductivity first and second drain regions 321 and 323 mayinclude a high concentration of phosphorus (P) atoms deposited therein.Embodiments, however, are not limited to this example. In otherembodiments, the laterally oriented access devices 330, e.g.,transistors, may be of a p-type conductivity construction in which casethe impurity, e.g., dopant, conductivity types would be reversed.

As shown in the example embodiment of FIG. 3 , the first source/drainregion 321 may occupy an upper portion in the body 326 of the laterallyoriented access devices 330, e.g., transistors. For example, the firstsource/drain region 321 may have a bottom surface 324 within the body326 of the laterally oriented access device 330 which is located higher,vertically in the third direction (D3) 311, than a bottom surface of thebody 326 of the laterally, horizontally oriented access device 330. Assuch, the laterally, horizontally oriented transistor 330 may have abody portion 326 which is below the first source/drain region 321 and isin electrical contact with the body contact, e.g., 295 shown in FIG. 2 .Further, as shown in the example embodiment of FIG. 3 , a digit line,e.g., 307-1, analogous to the digit lines 207-1, 207-2, . . . , 207-P inFIG. 2 and 107-1, 107-2 , . . . , 107-P shown in FIG. 1 , may disposedon a top surface 322 of the first source/drain region 321 andelectrically coupled thereto.

As shown in the example embodiment of FIG. 3 , an access line, e.g.,303-1, analogous to the access lines 203-1, 203-2, . . . , 203-Q in FIG.2 and 103-1, 103-2 , . . . , 103-Q in FIG. 1 , may be verticallyextending in the third direction (D3) 311 adjacent sidewall of thechannel region 325 portion of the body 326 to the laterally orientedaccess devices 330, e.g., transistors horizontally conducting betweenthe first and the second source/drain regions 321 and 323 along thesecond direction (D2) 305. A gate dielectric material 304 may beinterposed between the access line 303-1 (a portion thereof forming agate to the laterally oriented access devices 330, e.g., transistors)and the channel region 325. The gate dielectric material 304 mayinclude, for example, a high-k dielectric material, a silicon oxidematerial, a silicon nitride material, a silicon oxynitride material,etc., or a combination thereof. Embodiments are not so limited. Forexample, in high-k dielectric material examples the gate dielectricmaterial 304 may include one or more of hafnium oxide, hafnium siliconoxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide,tantalum oxide, titanium oxide, barium strontium titanium oxide, bariumtitanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide,lead scandium tantalum oxide, lead zinc niobite, etc.

FIG. 4A is a cross-sectional view, at one stage of a fabrication processfor a semiconductor device, such as illustrated in FIGS. 1-3 , inaccordance with a number of embodiments of the present disclosure.However, embodiments are not so limited. For instance, one or moreembodiments provide that the semiconductor devices having verticallyoriented access devices and horizontally oriented access lines. Asdiscussed further herein, the semiconductor device includes an arrayregion and a periphery region. FIGS. 4A-4K illustrate a portion of thearray region. As used herein, an “array region” refers to a regionhaving memory cells, e.g., vertically stacked memory cells. As usedherein, a “periphery region” refers to a region having peripheralcircuitry such as driver circuitry, decoders, sense amplifiers, etc.that can be used to access the memory cells in association with readingand/or writing data, for instance.

In the example embodiment shown in the example of FIG. 4A, the methodcomprises depositing alternating layers of a first dielectric material,430-1, 430-2, . . . , 430-N (collectively referred to as firstdielectric material 430), a semiconductor material, 432-1, 432-2, . . ., 432-N (collectively referred to as semiconductor material 432), and asecond dielectric material, 433-1, 433-2, . . . , 433-N (collectivelyreferred to as second dielectric 433), in repeating iterations to form avertical stack 401 on a working surface of a semiconductor substrate400. As shown in FIG. 4A, the vertical stack 401 includes an arrayregion 460 and a periphery region 462. The alternating materials in therepeating, vertical stack 401 may be separated from the substrate 400 byan insulator material 420. In one embodiment, the first dielectricmaterial 430 can be deposited to have a thickness, e.g., vertical heightin the third direction (D3), in a range of twenty (20) nanometers (nm)to sixty (60) nm. In one embodiment, the semiconductor material 432 canbe deposited to have a thickness, e.g., vertical height, in a range oftwenty (20) nm to one hundred (100) nm. In one embodiment, the seconddielectric material 433 can be deposited to have a thickness, e.g.,vertical height, in a range of ten (10) nm to thirty (30) nm.Embodiments, however, are not limited to these examples. As shown inFIG. 4 , a vertical direction 411 is illustrated as a third direction(D3), e.g., z-direction in an x-y-z coordinate system, analogous to thethird direction (D3), among first, second and third directions, shown inFIGS. 1-3 . Additionally, while FIG. 4A illustrates both the firstdielectric material 430-1 etc. and the second dielectric material 433-1are utilized, one or more embodiments provide that vertical stack 401does not include both of these dielectric materials. For instance, thevertical stack 401 may not include the first dielectric material 430-1etc.; for such embodiments, the vertical stack 401 will include thesecond dielectric material 433-1 etc. and the semiconductor material,432-1 etc., but not the first dielectric material 430-1. Alternatively,the vertical stack 401 may not include the second dielectric material433-1 etc.; for such embodiments, the vertical stack 401 will includethe first dielectric material 430-1 etc. and the semiconductor material,432-1 etc., but not the second dielectric material 433-1 etc.

In some embodiments the first dielectric material, 430-1, 430-2, . . . ,430-N, may be an interlayer dielectric (ILD). By way of example, and notby way of limitation, the first dielectric material, 430-1, 430-2, . . ., 430-N, may comprise an oxide material, e.g., SiO₂. In another examplethe first dielectric material, 430-1, 430-2, . . . , 430-N, may comprisea silicon nitride (Si₃N₄) material (also referred to herein as “SiN”).In another example the first dielectric material, 430-1, 430-2, . . . ,430-N, may comprise a silicon oxy-carbide (SiO_(x)C_(y)) material. Inanother example the first dielectric material, 430-1, 430-2, . . . ,430-N, may include silicon oxy-nitride (SiO_(x)N_(y)) material (alsoreferred to herein as “SiON”), and/or combinations thereof. Embodimentsare not limited to these examples.

In some embodiments the semiconductor material, which may also bereferred to as a sacrificial material, as portions of this material maybe selectively removed as discussed herein, 432-1, 432-2, . . . , 432-N,may comprise a silicon (Si) material in a polycrystalline and/oramorphous state. The semiconductor material, 432-1, 432-2, . . . ,432-N, may be a low doped, p-type (p−) silicon material. Thesemiconductor material, 432-1, 432-2, . . . , 432-N, may be formed bygas phase doping boron atoms (B), as an impurity dopant, at a lowconcentration to form the low doped, p-type (p−) silicon material. Thelow doped, p-type (p−) silicon material may be a polysilicon material.Embodiments, however, are not limited to these examples.

In some embodiments, the second dielectric material, 433-1, 433-2, . . ., 433-N, may be an interlayer dielectric (ILD). By way of example, andnot by way of limitation, the second dielectric material, 433-1, 433-2,. . . , 433-N, may comprise a nitride material. The nitride material maybe a silicon nitride (Si₃N₄) material (also referred to herein as“SiN”). In another example the second dielectric material, 433-1, 433-2,. . . , 433-N, may comprise a silicon oxy-carbide (SiOC) material. Inanother example the second dielectric material, 433-1, 433-2, . . . ,433-N, may include silicon oxy-nitride (SiON), and/or combinationsthereof. Embodiments are not limited to these examples. However,according to embodiments, the second dielectric material, 433-1, 433-2,. . . , 433-N, is purposefully chosen to be different in material orcomposition than the first dielectric material, 430-1, 430-2, . . . ,430-N, such that a selective etch process may be performed on one of thefirst and second dielectric layers, selective to the other one of thefirst and the second dielectric layers, e.g., the second SiN dielectricmaterial, 433-1, 433-2, . . . , 433-N, may be selectively etchedrelative to the semiconductor material, 432-1, 432-2, . . . , 432-N, anda first oxide dielectric material, 430-1, 430-2, . . . , 430-N.

The repeating iterations of alternating first dielectric material,430-1, 430-2, . . . , 430-N layers, semiconductor material, 432-1,432-2, . . . , 432-N layers, and second dielectric material, 433-1,433-2, . . . , 433-N layers may be deposited according to a fabricationprocess for a semiconductor device such as chemical vapor deposition(CVD). Embodiments, however, are not limited to this example and othersuitable fabrication techniques may be used to deposit the alternatinglayers of a first dielectric material, a semiconductor material, and asecond dielectric material, in repeating iterations to form the verticalstack 401.

The layers may occur in repealing iterations vertically. In the exampleof FIG. 4A, three tiers, numbered 1, 2, and 3, of the repeatingiterations are shown. For example, the stack may include: a firstdielectric material 430-1, a semiconductor material 432-1, a seconddielectric material 433-1, a third dielectric material 430-2, a secondsemiconductor material 432-2, a fourth dielectric material 433-2, afifth dielectric material 430-3, a third semiconductor material 432-3,and a sixth dielectric material 433-3. Embodiments, however, are notlimited to this example and more or fewer repeating iterations may beincluded.

FIG. 4B is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

According to embodiments, the fabrication process described in FIGS.4B-4K can occur after an elongated pillar extending in the seconddirection and access line formation such as shown in FIGS. 5A-6E havebeen performed.

As shown in FIG. 4B, a vertical opening 471 may be formed through thelayers within the vertically stacked memory cells to expose verticalsidewalls in the vertical stack. The vertical opening 471 may be formedthrough the repeating iterations of the oxide material 430, thesemiconductor material 432, and the nitride material 433. As such, thevertical opening 471 may be formed through the first oxide material430-1, the first semiconductor material 432-1, the first nitridematerial 433-1, the second oxide material 430-2, the secondsemiconductor material 432-2, the second nitride material 433-2, thethird oxide material 430-3, the third semiconductor material 432-3, andthe third nitride material 433-3. Embodiments, however, are not limitedto the single vertical opening shown in FIG. 4B. Multiple verticalopenings may be formed through the layers of materials. The verticalopening 471 may be formed to expose vertical sidewalls in the verticalstack.

FIG. 4C is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device such as illustrated in FIGS. 1-3 , inaccordance with a number of embodiments of the present disclosure.

An etchant may be flowed into the vertical opening 471 to selectivelyetch the second dielectric material 433. For example, an etchant may beflowed into the vertical opening 471 to selectively etch the nitridematerial 433. The etchant may target all iterations of the seconddielectric material 433 within the stack. As such, the etchant maytarget the first nitride material 433-1, the second nitride material433-2, and the third nitride material 433-3 within the stack.

The selective etchant process may consist of one or more etchchemistries selected from an aqueous etch chemistry, a semi-aqueous etchchemistry, a vapor etch chemistry, or a plasma etch chemistries, amongother possible selective etch chemistries. For example, a dry etchchemistry of oxygen (O₂) or O₂ and sulfur dioxide (SO₂) (O₂/SO₂) may beutilized. A dry etch chemistries of O₂ or of O₂ and nitrogen (N₂)(O₂/N₂) may be used to selectively etch the second dielectric material433. Alternatively, or in addition, a selective etch to remove thesecond dielectric material 433 may comprise a selective etch chemistryof phosphoric acid (H₃PO₄) or hydrogen fluoride (HF) and/or dissolvingthe second dielectric material 433 using a selective solvent, forexample NH₄OH or HF, among other possible etch chemistries or solvents.The etchant process may cause an oxidization of only the nitridematerial 433. As shown in the example of FIG. 4C, the etchant processmay form a protective oxide coating, e.g., second oxide material 434, onthe semiconductor material 432. Hence, the first dielectric material 430and the semiconductor material 432 may be left intact during theselective etchant process. For example, the selective etchant processmay etch a portion of the nitride material 433, while not removing theoxide material 430 and the polysilicon material 432.

As noted, the semiconductor material 432 may be protected by a secondoxide material 434 formed on the semiconductor material 432 during theselective etchant process. The second oxide material 434 may be presenton all iterations of the semiconductor material 432. For example, thesecond oxide material 434 may be present on a sidewall to the firstsemiconductor material 432-1, the second semiconductor material 432-2,and the third semiconductor material 432-3, etc., in the verticalopening 471 within the stack.

FIG. 4D is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

The selective etchant process may etch the nitride material 433 to forma first horizontal opening 473. The selective etchant process may beperformed such that the first horizontal opening 473 has a length ordepth (D1) 476 a first distance 476 from the vertical opening 471. Thedistance (D1) 476 may be controlled by controlling time, composition ofetchant gas, and etch rate of a reactant gas flowed into the verticalopening 471, e.g., rate, concentration, temperature, pressure, and timeparameters. As such, the nitride material 433 may be etched a firstdistance 476 from the vertical opening 471. The selective etch may beisotropic, but selective to the second dielectric material 433,substantially stopping on the first dielectric material 430 and thesemiconductor material. Thus, in one example embodiment, the selectiveetchant process may remove substantially all of the nitride material 433from a top surface of the semiconductor material 432 to a bottom surfaceof the first dielectric material, e.g., oxide material, in a layer abovewhile etching horizontally a distance (D1) 476 from the vertical opening471 between the semiconductor material 432 and the oxide material 430.In this example the horizontal opening 473 will have a height (H1) 435substantially equivalent to a thickness, to which the second dielectriclayer 433, e.g., nitride material, was deposited. Embodiments, however,are not limited to this example. As described herein, the selectiveetchant process may etch the nitride material 433 to a first distance(D1) 476 and to a height (H1) 435.

FIG. 4E is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

A first source/drain region 475 may be formed by gas phase doping adopant into a top surface portion of the semiconductor material 432 viathe horizontal opening 473. Gas phase doping may be used to achieve ahighly isotropic e.g., non-directional doping. In another example,thermal annealing with doping gas, such as phosphorous may be used witha high energy plasma assist to break the bonding. Embodiments are not solimited and other suitable fabrication techniques may be utilized. Awidth of the first source/drain region 475, doped into the top surfaceportion of the semiconductor material 432, may be substantially formedall along the first distance (D1) 476 of the first horizontal opening473 from the vertical opening 471. The source/drain region 475 may beformed by gas phase doping phosphorus (P) atoms, as impurity dopants, ata high plasma energy such as PECVD to form a high concentration, n-typedoped (n+) region in the top surface of the semiconductor material 432.

FIG. 4F is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

A conductive material 477 may be conformally deposited into a portion ofthe vertical opening 471, e.g., using a chemical vapor deposition (CVD)process, such that the conductive material may also be deposited intothe first horizontal opening 473. In some embodiments, the conductivematerial 477 may comprise a titanium nitride (TiN) material. In someembodiments the conductive material 477 may be tungsten (W). In thisexample, some embodiments may include forming the tungsten (W) materialaccording to a method as described U.S. patent application Ser. No.16/942,108, for instance. The conductive material 477 may form alaterally oriented digit line.

FIG. 4G is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

The conductive material 477 may be recessed back in the horizontalopening 473, e.g., etched away from the vertical opening 471 using anatomic layer etching (ALE) or other suitable technique. In someexamples, the conductive material 477 may be etched back in thehorizontal opening 473 a second distance (D2) 483 from the verticalopening 471. The conductive material 477 may be selectively etched,leaving the oxide material 430, a portion of the conductive material477, the semiconductor material 432, and the source/drain region 475intact. The conductive material 477 may be etched using a third etchantprocess. In some embodiments, the conductive material 477 may be etchedusing an atomic layer etching (ALE) process. In some embodiments, theconductive material 477 may be etched using an isotropic etch process.The conductive material 477 may be recessed the second distance (D2) 483back in the horizontal opening 473 to remain in direct electricalcontact on a top surface of the first source/drain region 475 formed inthe semiconductor material 432. As such, the conductive material 477remains in electrical contact with the source/drain region 475 and mayform part of an integral, horizontally oriented, conductive digit line,e.g., digit lines 107, 207, and 307 in FIGS. 1-3 respectively.

FIG. 4H is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

As shown in FIG. 4H, the oxide material protecting the sidewalls ofsemiconductor material (illustrated as 434 in FIGS. 4C-4G) in thevertical opening 471, a portion of the first source/drain region 475,and a first portion 478 of the semiconductor material 432 beneath thefirst source/drain region 475 may be selectively etched away to allowfor formation of a body contact to a body region of the horizontalaccess device. In this example, a portion of the source/drain region 475and a top portion, e.g., first portion 478, of the semiconductormaterial 432 beneath the first source/drain region 475 may also beetched back to a second distance (D2) 483 from the vertical opening 471.The etch may be performed using a fourth etchant process, e.g., using anatomic layer etching (ALE) or other suitable technique. In someembodiments, the source/drain region 475 may be etched to the samehorizontal distance (D2) 483 from the vertical opening 471 as theconductive material 477.

Thus, a second horizontal opening 472 may be formed by the etching ofthe portion of the source/drain region 475 and the top surface, e.g.,478, of the semiconductor material 432 beneath the first source/drainregion 475 the second horizontal distance (D2) 483 from the verticalopening 471. As such, the second horizontal openings 472 may have asecond vertical height (H2) 485. The second vertical height (H2) 485 maybe greater, e.g., taller vertically, than a combination of the height(H1) 435 of the first horizontal opening 473 formed in the seconddielectric material, e.g., nitride material, and the height, e.g., depthof gas phase doping into the top surface of the semiconductor material432, of the source/drain region 475. For example, the second height (H2)485 may also include the height of the top portion, e.g., 478, of thesemiconductor material 432 that was etched away. Thus, the seconddistance (D2) 483 may be shorter that the first distance (D1) 476, butthe second height 485 may be taller than the first height (illustratedas H1 in FIGS. 4D-4E).

FIG. 4I is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

As shown in FIG. 4I, a third dielectric material 474 is conformallydeposited, e.g., using a CVD process, into the vertical opening 471 andmay conformally fill the vertical opening 471 the second horizontalopening (illustrated as 472 in FIGS. 4D-4H). The third dielectricmaterial 474 may be horizontally adjacent to the conductive material477, e.g., horizontal, conductive digit line extending in the firstdirection (D1) 109 in FIG. 1 , the source/drain region 475, and thefirst portion of the low doped, e.g., p-type, lowed doped (p−),semiconductor material 432. For example, in some embodiments, the thirddielectric material 474 may be below the first dielectric material 430and in direct contact with the conductive material 477, the source/drainregion 475, and the first portion of the low doped semiconductormaterial 432. Embodiments, however, are not limited to this example.

The third dielectric material 474 may be the same material or adifferent material as the second dielectric material 433. For example,the second dielectric material may be Si₂N₃ and the third dielectricmaterial may also be Si₃N₄. In another example the third dielectricmaterial 474 may comprise a silicon dioxide (SiO₂) material. In anotherexample the third dielectric material 474 may comprise a siliconoxy-carbide (SiO_(x)C_(y)) material. In another example the thirddielectric material 474 may include silicon oxy-nitride (SiO_(x)N_(y)),and/or combinations thereof. Embodiments are not limited to theseexamples.

FIG. 4J is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

The third dielectric material 474 may be recessed back to remove fromthe first vertical opening 471 and maintain the first vertical opening471 to allow for deposition of a conductive material (shown in FIG. 4K)to form a direct, electrical contact between such conductive materialdeposited within the vertical opening 471 and a second portion 479 ofthe low doped, e.g., p-type, low doped (p−), semiconductor material 432,e.g., body region contact, of the horizontally oriented access device,e.g., 901 in FIG. 9 , within the vertical stack. In some embodiments,the third dielectric material 474 may be etched away from the verticalopening 471 to expose the sidewalls of the first dielectric material430, the third dielectric material 474, and a second portion 479 of thesemiconductor material 432.

FIG. 4K is a cross-sectional view, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.

As shown in FIG. 4K, a conductive material 495 is deposited into thevertical opening 471 to form a direct, electrical contact with thesecond portion 479 of the low doped, e.g., p-type, low doped (p−),semiconductor material 432. In some embodiments, the conductive materialmay be a metal such as tungsten (W). Embodiments, however, are not solimited. In some embodiments, the conductive material 495 is a highdoped, e.g., p-type, high doped (p+), semiconductor material which maybe deposited into the vertical opening 471. In this example, the highdoped semiconductor material 495 may be a high doped, p-type (p+)silicon material. The high doped, p-type (p+) silicon material 495 maybe a polysilicon material. In one example, forming the conductive bodycontact comprises depositing a degenerate semiconductor material. Asused herein, a degenerate semiconductor material is intended to mean asemiconductor material, such as polysilicon, containing a high level ofdoping with significant interaction between dopants, e.g., phosphorous(P), boron (B), etc. Non-degenerate semiconductors, by contrast, containmoderate levels of doping, where the dopant atoms are well separatedfrom each other in the semiconductor host lattice with negligibleinteraction.

In some examples, the high doped semiconductor material 495 may be ahigh doped, p-type (p+) silicon-germanium (SiGe) material. The SiGematerial, may be deposited in to the vertical opening 471 at arelatively lower temperature. Embodiments, however, are not limited tothese examples. The high doped, p-type (p+) silicon material 495 mayform a conductive body contact with the second portion 479 of thesemiconductor material 432.

The high doped, p-type (p+) silicon material 495 may reduce holesgenerated by gate-induced drain leakage (GIDL) during operation of thelaterally oriented access devices. The high doped, p-type (p+) siliconmaterial 495 may control channel potential within the semiconductormaterial 432 by controlling hole formation within the semiconductormaterial 432. For example, holes formation which may occur between thefirst source/drain region 475, the high doped (p+) polysilicon material,and a body region of the horizontally oriented access device if thefirst source/drain region 475 were not electrically isolated from theconductive material 495 by the third dielectric material 474.

FIG. 5A illustrates an example method, at another stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosureFIG. 5A illustrates a top down view of a semiconductor structure, at aparticular point in time, in the fabrication process, according to oneor more embodiments. As discussed further herein, the semiconductordevice includes an array region and a periphery region. FIGS. 5A-5Billustrate a portion of the array region. In the example embodimentshown in the example of FIG. 5A, the method comprises using an etchantprocess to form a plurality of first vertical openings 500, having afirst horizontal direction (D1) 509 and a second horizontal direction(D2) 505, through the vertical stack to the substrate. In one example,as shown in FIG. 5A, the plurality of first vertical openings 500 areextending predominantly in the second horizontal direction (D2) 505 andmay form elongated vertical, pillar columns 513 with sidewalls 514 inthe vertical stack. The plurality of first vertical openings 500 may beformed using photolithographic techniques to pattern a photolithographicmask 535, e.g., to form a hard mask (HM), on the vertical stack prior toetching the plurality of first vertical openings 500.

FIG. 5B is a cross sectional view, taken along cut-line A-A′ in FIG. 5A,showing another view of the semiconductor structure at a particular timein the fabrication process for a semiconductor device. The crosssectional view shown in FIG. 5B shows the repealing iterations ofalternating layers of a first dielectric material, 530-1, 530-2, . . . ,530-N, a semiconductor material, 532-1, 532-2, . . . , 532-N, and asecond dielectric material, 533-1, 533-2, . . . , 533-N, on asemiconductor substrate 500 to form the vertical stack, e.g. 401 asshown in FIG. 4 . FIG. 5B illustrates that a conductive material, 540-1,540-2, . . . , 540-4, may be formed on a gate dielectric material 538 inthe plurality of first vertical openings 500. By way of example and notby way of limitation, a gate dielectric material 538 may be conformallydeposited in the plurality of first vertical openings 500 using achemical vapor deposition (CVD) process, plasma enhanced CVD (PECVD),atomic layer deposition (ALD), or other suitable deposition process, tocover a bottom surface and the vertical sidewalls of the plurality offirst vertical openings. The gate dielectric 538 may be deposited to aparticular thickness (t1) as suited to a particular design rule, e.g., agate dielectric thickness of approximately 10 nanometers (nm).Embodiments, however, are not limited to this example. By way ofexample, and not by way of limitation, the gate dielectric 538 maycomprise a silicon dioxide (SiO₂) material, aluminum oxide (Al₂O₃)material, high dielectric constant (k), e.g., high-k, dielectricmaterial, and/or combinations thereof as also described in FIG. 3 .

Further, as shown in FIG. 5B, a conductive material, 540-1, 540-2, . . ., 540-4, may be conformally deposited in the plurality of first verticalopenings 500 on a surface of the gate dielectric material 538. By way ofexample, and not by way of limitation, the conductive material, 540-1,540-2, . . . , 540-4, may be conformally deposited in the plurality offirst vertical openings 500 on a surface of the gate dielectric material538 using a chemical vapor deposition process (CVD), plasma enhanced CVD(PECVD), atomic layer deposition (ALD), or other suitable depositionprocess, to cover a bottom surface and the vertical sidewalls of theplurality of first vertical openings over the gate dielectric 538. Theconductive material, 540-1, 540-2, . . . , 540-4, may be conformallydeposited to a particular thickness (t2) to form vertically orientedaccess lines, such as shown as access lines 103-1, 103-2, . . . , 103Q(which also may be referred to a wordlines) shown in FIG. 1 , et. seq.,and as suited to a particular design rule. For example, the conductivematerial, 540-1, 540-2, . . . , 540-4, may be conformally deposited to athickness of approximately 20 nanometers (nm). Embodiments, however, arenot limited to this example. By way of example, and not by way oflimitation, the conductive material, 540-1, 540-2, . . . , 540-4, maycomprise one or more of a doped semiconductor, e.g., doped silicon,doped germanium, etc., a conductive metal nitride, e.g., titaniumnitride, tantalum nitride, etc., a metal, e.g., tungsten (W), titanium(Ti), tantalum (Ta), ruthenium (Ru), cobalt (Co), molybdenum (Mo), etc.,and/or a metal-semiconductor compound, e.g., tungsten silicide, cobaltsilicide, titanium silicide, etc. and/or some other combination thereofas also described in FIG. 3 .

As shown in FIG. 5B, the conductive material, 540-1, 540-2, . . . ,540-4, may be recessed back to remain only along the vertical sidewallsof the elongated vertical, pillar columns, now shown as 542-1, 542-2,and 542-3 in the cross-sectional view of FIG. 5B. The plurality ofseparate, vertical access lines formed from the conductive material,540-1, 540-2, . . . , 540-4, may be recessed back by using a suitableselective, anisotropic etch process remove the conductive material,540-1, 540-2, . . . , 540-4, from a bottom surface of the first verticalopenings, e.g., 500 in FIG. 5A, exposing the gate dielectric 538 on thebottom surface to form separate, vertical access lines, 540-1, 540-2, .. . , 540-4. As shown in FIG. 5B, a dielectric material 539, such as anoxide or other suitable spin on dielectric (SOD), may then be depositedin the first vertical openings 500, using a process such as CVD, to fillthe first vertical openings 500. The dielectric may be planarized to atop surface of the hard mask 535 of the vertical semiconductor stack,using chemical mechanical planarization (CMP) or other suitablefabrication technique. A subsequent photolithographic material 536,e.g., hard mask, may be deposited using CVD and planarized using CMP tocover and close the first vertical openings 500 over the separate,vertical access lines, 540-1, 540-2, . . . , 540-4. Similarsemiconductor process techniques may be used at other points of thefabrication process described herein. However, as mentioned embodimentsare not so limited. For instance, a number of processes described hereinmay be utilized to form semiconductor devices having horizontal accesslines. When horizontal access lines are utilized, semiconductor devicesmay comprise vertical digit lines.

FIG. 6A illustrates an example method, at another stage of a fabricationprocess for a semiconductor device, for forming arrays of verticallystacked memory cells, such as illustrated in FIGS. 1-3 , in accordancewith a number of embodiments of the present disclosure. FIG. 6Aillustrates a top down view of a semiconductor structure, at aparticular point in time, in the fabrication process, according to oneor more embodiments. As discussed further herein, the semiconductordevice includes an array region and a periphery region, e.g., as shownin FIG. 7A. FIGS. 6A-6E illustrate a portion of the array region, i.e.the region where transistors and access lines are formed. Asillustrated, FIG. 6A includes the array region 660. In the exampleembodiment of FIG. 6A, the method comprises using a photolithographicprocess to pattern the photolithographic mask 636, 536 in FIG. 5B. Themethod in FIG. 6A, further illustrates using a selective, isotropicetchant process remove portions of the exposed conductive material,640-1, 640-2, . . . , 640-N, 640-(N+1), . . . , 640-(Z−1), and 640-Z, toseparate and individually form the plurality of separate, verticalaccess lines, 640-1, 640-2, . . . , 640-N, 640-(N+1), . . . , 640-(Z−1),and 640-Z, e.g., access lines 103-1, 103-2, . . . , 103-Q in FIG. 1 ,et. seq. Hence the plurality of separate, vertical access lines, 640-1,640-2, . . . , 640-N, 640-(N+1), . . . , 640-(Z−1), and 640-Z, are shownalong the sidewalls of the elongated vertical, pillar columns, e.g.,along sidewalls of the elongated vertical, pillar columns 542-1, 542-2,and 542-3 in the cross-sectional view of FIG. 5B.

As shown in the example of FIG. 6A, the exposed conductive material,640-1, 640-2, . . . , 640-N, 640-(N+1), . . . , 640-(Z−1), and 640-Z,may be removed back to the gate dielectric material 638 in the firstvertical openings, e.g., 500 in FIG. 5A, using a suitable selective,isotropic etch process. As shown in FIG. 6A, a subsequent dielectricmaterial 641, such as an oxide or other suitable spin on dielectric(SOD), may then be deposited to fill the remaining openings from wherethe exposed conductive material, 640-1, 640-2, . . . , 640-N, 640-(N+1),. . . , 640-(Z−1), and 640-Z, was removed using a process such as CVD,or other suitable technique. The dielectric material 641 may beplanarized to a top surface of the previous hard mask 635 of thevertical semiconductor stack, e.g., 401 as shown in FIG. 4 , using aprocess such as CMP, or other suitable technique. In some embodiments, asubsequent photolithographic material 537, e.g., hard mask, may bedeposited using CVD and planarized using CMP to cover and close theplurality of separate, vertical access lines, 640-1, 640-2, . . . ,640-N, 640-(N+1), . . . , 640-(Z−1), and 640-Z, over a working surfaceof the vertical semiconductor stack, 401 in FIG. 4 , leaving theplurality of separate, vertical access lines, 640-1, 640-2, . . . ,640-N, 640-(N+1), . . . , 640-(Z−1), and 640-Z, protected along thesidewalls of the elongated vertical, pillar columns. Embodiments,however, are not limited to these process examples.

FIG. 6B illustrates a cross sectional view, taken along cut-line A-A′ inFIG. 6A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 6B isaway from the plurality of separate, vertical access lines, 640-1,640-2, . . . , 640-N, 640-(N+1), . . . , 640-(Z−1), and shows therepeating iterations of alternating layers of a first dielectricmaterial, 630-1, 630-2, . . . , 630-N, a semiconductor material, 632-1,632-2, . . . , 632-N, and a second dielectric material, 633-1, 633-2, .. . , 633-N, on a semiconductor substrate 600 to form the verticalstack, e.g. 401 as shown in FIG. 4 . As shown in FIG. 6B, a verticaldirection 611 is illustrated as a third direction (D3), e.g.,z-direction in an x-y-z coordinate system, analogous to the thirddirection (D3) 111, among first, second and third directions, shown inFIGS. 1-3 . The plane of the drawing sheet, extending right and left, isin a first direction (D1) 609. In the example embodiment of FIG. 6B, thedielectric material 641 is shown filling the vertical openings on theresidual gate dielectric 638 deposition. The hard mask 637, describedabove, caps the illustrated structure.

FIG. 6C illustrates a cross sectional view, taken along cut-line B-B′ inFIG. 6A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 6C isillustrated extending in the second direction (D2) 605 along an axis ofthe repeating iterations of alternating layers of a first dielectricmaterial, 630-1, 630-2, . . . , 630-N, a semiconductor material, 632-1,632-2, . . . , 632-N, and a second dielectric material, 633-1, 633-2, .. . , 633-N, along and in which the horizontally oriented access devicesand horizontally oriented storage nodes, e.g., capacitor cells, can beformed within the layers of semiconductor material, 632-1, 632-2, . . ., 632-N. In FIG. 6C, a neighboring, opposing vertical access line 640-3is illustrated by a dashed line indicating a location set in from theplane and orientation of the drawing sheet.

FIG. 6D illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 6A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 6D isillustrated extending in the second direction (D2) 605 along an axis ofthe repeating iterations of alternating layers of a first dielectricmaterial, 630-1, 630-2, . . . , 630-N, a semiconductor material, 632-1,632-2, . . . , 632-N, and a second dielectric material, 633-1, 633-2, .. . , 633-N, outside of a region in which the horizontally orientedaccess devices and horizontally oriented storage nodes, e.g., capacitorcells, will be formed within the layers of semiconductor material,632-1, 632-2, . . . , 632-N. In FIG. 6C, the dielectric material 641 isshown filling the space between the horizontally oriented access devicesand horizontally oriented storage nodes, which can be spaced along afirst direction (D1), extending into and out from the plane of thedrawings sheet, for a three dimensional array of vertically orientedmemory cells. At the left end of the drawing sheet is shown therepeating iterations of alternating layers of a first dielectricmaterial, 630-1, 630-2, . . . , 630-N, a semiconductor material, 632-1,632-2, . . . , 632-N, and a second dielectric material, 633-1, 633-2, .. . , 633-N, at which location a horizontally oriented digit line, e.g.,digit lines 107-1, 107-2, . . . , 107-P shown in FIG. 1 , et. seq., canbe integrated to form electrical contact with the second source/drainregions or digit line conductive contact material, described in moredetail below.

FIG. 6E illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 6A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 6E isillustrated, right to left in the plane of the drawing sheet, extendingin the first direction (D1) 609 along an axis of the repeatingiterations of alternating layers of a first dielectric material 630-1,630-2, . . . , 630-N, a semiconductor material, 632-1, 632-2, . . . ,632-N, and a second dielectric material, 633-1, 633-2, . . . , 633-N,intersecting across the plurality of separate, vertical access lines,640-1, 640-2, . . . , 640-N, 640-(N+1), . . . , 640-(Z−1), andintersecting regions of the semiconductor material, 632-1, 632-2, . . ., 632-N, in which a channel region may be formed, separated from theplurality of separate, vertical access lines, 640-1, 640-2, . . . ,640-N, 640-(N+1), . . . , 640-(Z−1), by the gate dielectric 638. In FIG.6E, the first dielectric fill material 639 is shown separating the spacebetween neighboring horizontally oriented access devices andhorizontally oriented storage nodes, which may be formed extending intoand out from the plane of the drawing sheet as described in more detailbelow, and can be spaced along a first direction (D1) 609 and stackedvertically in arrays extending in the third direction (D3) 611 in thethree dimensional (3D) memory.

FIG. 7A illustrates an example method, at another stage of a fabricationprocess for a semiconductor device, for forming arrays of verticallystacked memory cells, such as illustrated in FIGS. 1-3 , in accordancewith a number of embodiments of the present disclosure. FIG. 7Aillustrates a top down view of a semiconductor structure, at aparticular point in time, in the fabrication process, according to oneor more embodiments. As illustrated in FIG. 7A, semiconductor structureincludes an array region 760 and a periphery region 762. In the exampleembodiment of FIG. 7A, the method comprises using a photolithographicprocess to pattern the photolithographic masks 735, 736 and/or 737,e.g., 635, 636, and/or 637 in FIGS. 6A-6E. The method in FIG. 7A,further illustrates using one or more etchant processes to form avertical opening 751 in a storage node region 750 (and 744 in FIGS. 7Aand 7C) through the vertical stack and extending predominantly in thefirst horizontal direction (D1) 709. The one or more etchant processesforms a vertical opening 751 to expose third sidewalls in the repeatingiterations of alternating layers of a first dielectric material, 730-1,730-2, . . . , 730-N, a semiconductor material, 732-1, 732-2, . . . ,732-N, and a second dielectric material, 733-1, 733-2, . . . , 733-N, inthe vertical stack, shown in FIGS. 7B-7E, adjacent a second region ofthe semiconductor material. Also, one or more etchant processes form anumber of vertical openings 764 in the periphery region. The verticalopenings 764 in the periphery region 762 are similar to the verticalopening 751 in the array region 760. The etchant processes to formvertical openings 751/764 can be performed concurrently. Other numeratedcomponents may be analogous to those shown and discussed in connectionwith FIG. 6 .

In some embodiments, this process is performed before the fabricationprocess described in connection with FIGS. 4A-4K. However, theembodiment shown in FIGS. 7B-7F illustrate a sequence in which thestorage node, e.g., capacitor, fabrication process is performed “after”the digit line 777 and first source/drain region formation, described inconnection with FIGS. 4A-4K, have already been performed, e.g., digitline formation first. Here, the digit line 777 may be illustrated alongthe plurality of separate, vertical access lines 740.

According to an example embodiment, shown in FIGS. 7B-7F, the methodcomprises forming a second vertical opening 751/764 in the verticalstack (401 in FIG. 4A) and selectively etching the second region 744 ofthe semiconductor material, 732-1, 732-2, . . . , 732-N, to form asecond horizontal opening 779 a second horizontal distance (D2 opening)back from the vertical opening 751 in the vertical stack (401 in FIG.4A). According to embodiments, selectively etching the second region 744of the semiconductor material, 732-1, 732-2, . . . , 732-N can compriseusing an atomic layer etching (ALE) process. As will be explained morein connection with FIG. 7C, a second source/drain region 778 can beformed in the semiconductor material, 732-1, 732-2, . . . , 732-N at adistal end of the second horizontal openings 779 from the verticalopening.

FIG. 7B illustrates a cross sectional view, taken along cut-line A-A′ inFIG. 7A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 7B isaway from the plurality of separate, vertical access lines, 740-1,740-2, . . . , 740-N, 740-(N+1), . . . , 740-(Z−1), and shows repeatingiterations of alternating layers of a dielectric material, 730-1, 730-2,. . . , 730-(N+1), a semiconductor material, 732-1, 732-2, . . . ,732-N, and a second dielectric material, 733-1, 733-2, . . . , 733-Nseparated by an opening 751, on a semiconductor substrate 700 to formthe vertical stack. As shown in FIG. 7B, a vertical direction 711 isillustrated as a third direction (D3), e.g., z-direction in an x-y-zcoordinate system, analogous to the third direction (D3) 111, amongfirst, second and third directions, shown in FIGS. 1-3 . The plane ofthe drawing sheet, extending right and left, is in a first direction(D1) 709. In the example embodiment of FIG. 7B, the materials within thevertical stack—a dielectric material, 730-1, 730-2, . . . , 730-(N+1), asemiconductor material, 732-1, 732-2, . . . , 732-N, and a seconddielectric material, 733-1, 733-2, . . . , 733-N are extending into andout of the plane of the drawing sheet in second direction (D2) and alongan axis of orientation of the horizontal access devices and horizontalstorage nodes of the arrays of vertically stacked memory cells of thethree dimensional (3D) memory. Additionally, FIG. 7B illustrates avertical opening 764 formed in the periphery region 762.

FIG. 7C illustrates a cross sectional view, taken along cut-line B-B′ inFIG. 7A, showing another view of the array region 760 of thesemiconductor structure at this particular point in one example afabrication process of an embodiment of the present disclosure. Thecross sectional view shown in FIG. 7C is illustrated extending in thesecond direction (D2) 705, left and right along the plane of the drawingsheet, along an axis of the repeating iterations of alternating layersof a first dielectric material, 730-1, 730-2, . . . , 730-N, asemiconductor material, 732-1, 732-2, . . . , 732-N, and a seconddielectric material, 733-1, 733-2, . . . , 733-N, along and in which thehorizontally oriented access devices and horizontally oriented storagenodes, e.g., capacitor cells, can be formed within the layers ofsemiconductor material, 732-1, 732-2, . . . , 732-N.

In the example embodiment of FIG. 7C, a vertical opening 751 andhorizontal openings 779 are shown formed from the mask, patterning andetching process described in connection with FIG. 7A. As shown in FIG.7C, the semiconductor material, 732-1, 732-2, . . . , 732-N, in thesecond region 744 has been selectively removed to form the horizontalopenings 779. In one example, an atomic layer etching (ALE) process isused to selectively etch the semiconductor material, 732-1, 732-2, . . ., 732-N, and remove a second distance (D2 opening) back from thevertical opening 751. Horizontally oriented storage nodes, e.g.,capacitor cells, may be formed, as shown in FIGS. 8A-8E, later or first,relative to the fabrication process shown in FIGS. 4A-4K, in the secondhorizontal openings 779.

Also shown in FIG. 7C, the first source/drain region 775 may be formedby gas phase doping a dopant into a top surface portion of thesemiconductor material 732. In some embodiments, the first source/drainregion 775 may be adjacent to vertical access line 740. According to oneexample embodiment, as shown in FIG. 7C a second source/drain region 778may be formed by flowing a high energy gas phase dopant, such asPhosphorous (P) for an n-type transistor, into the second horizontalopenings 779 to dope the dopant in the semiconductor material, 732-1,732-2, . . . , 732-N, at a distal end of the second horizontal openings779 from the vertical opening 751. In one example, gas phase doping maybe used to achieve a highly isotropic e.g., non-directional doping, toform the second source/drain region 778 to a horizontally orientedaccess device in region 742. In another example, thermal annealing withdoping gas, such as phosphorous may be used with a high energy plasmaassist to break the bonding. Embodiments, however, are not so limitedand other suitable fabrication techniques may be utilized.

Conductive material 777 may be deposited adjacent second dielectricmaterial 733. The conductive material 777 may remain in directelectrical contact on a top surface of the first source/drain region775. As such, the conductive material 777 remains in electrical contactwith the source/drain region 775. In some embodiments, the thirddielectric material 774 may be below the first dielectric material 730while remaining in direct contact with the conductive material 777, thefirst source/drain region 775, and the first portion of the low dopedsemiconductor material 732. The third dielectric material 774 may form adirect, electrical contact with a high doped, p-type (p+) siliconmaterial 795, e.g., the body region contact of the horizontally orientedaccess device.

As discussed further herein, a first electrode, e.g., 861, forhorizontally oriented storage nodes are respectively to be coupled tothe second source/drain regions 778 of the horizontal access devices.These horizontally oriented storage nodes are formed in a secondhorizontal opening 779 extending in second direction (D2), left andright in the plane of the drawing sheet, a second distance (D2 opening)from the vertical opening 751 formed in the vertical stack, e.g., 401 inFIG. 4A, and along an axis of orientation of the horizontal accessdevices and horizontal storage nodes of the arrays of vertically stackedmemory cells of the three dimensional (3D) memory. In FIG. 7C, aneighboring, opposing vertical access line 740-3 is illustrated by adashed line indicating a location set inward from the plane andorientation of the drawing sheet.

FIG. 7D illustrates a portion of a cross sectional view, showing asection of the periphery region 762 at a particular point of afabrication process according to the present disclosure. As illustratedin FIG. 7D, a number of horizontal openings 766 are formed in theperiphery region 762. The horizontal openings 766 formed in theperiphery region 762 are formed concurrently with the horizontalopenings 779 in the array region 760. For example, processes, e.g. anetching process, discussed herein as utilized for the array region 760may also be utilized for the periphery region 762. Such processes may beutilized simultaneously for the array region 760 and the peripheryregion 762; however, embodiments are not so limited. For instance, anatomic layer etching (ALE) process used to selectively etch thesemiconductor material, 732-1, 732-2, . . . , 732-N, and form the secondhorizontal openings 779 shown in FIG. 7C, may also be used, e.g.simultaneously, to etch the semiconductor material, 732-1, 732-2, . . ., 732-N in periphery region 762 and form the horizontal openings 766shown in FIG. 7D. In other words, periphery capacitors in the peripheryregion 762 may be formed simultaneously as storage nodes, i.e. arraycapacitors, in the array region 760. One or more embodiments providethat the capacitors, e.g., in the periphery region 762 and the arrayregion 760, can be metal-insulator-metal (MIM) capacitors ormetal-ferroelectric-metal (MFM) capacitors.

FIG. 7E illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 7A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 7E isillustrated extending in the second direction (D2) 705, left and rightin the plane of the drawing sheet, along an axis of the repeatingiterations of alternating layers of a first dielectric material, 730-1,730-2, . . . , 730-N, a semiconductor material, 732-1, 732-2, . . . ,732-N, and a second dielectric material, 733-1, 733-2, . . . , 733-N,outside of a region in which the horizontally oriented access devicesand horizontally oriented storage nodes, e.g., capacitor cells, will beformed within the layers of semiconductor material, 732-1, 732-2, . . ., 732-N in the array region 760. At the left end of the drawing sheet isshown the repeating iterations of alternating layers of a firstdielectric material, 730-1, 730-2, . . . , 730-N, a semiconductormaterial, 732-1, 732-2, . . . , 732-N, and a second dielectric material,733-1, 733-2, . . . , 733-N, at which location a horizontally orienteddigit line, e.g., digit lines 107-1, 107-2, . . . , 107-P shown in FIG.1 , et. seq., can be integrated to form electrical contact with firstsource/drain regions or digit line conductive contact material describedabove in connection with FIGS. 4A-4K.

Again, while first and second source/drain region references are usedherein to denote two separate and distinct source/drain regions, it isnot intended that the source/drain region referred to as the “first”and/or “second” source/drain regions have some unique meaning. It isintended only that one of the source/drain regions is connected to adigit line, e.g., 107-2, and the other may be connected to a storagenode.

In some embodiments, a conductive material 777 may be illustratedadjacent second dielectric material 733. The conductive material 777 maybe adjacent dielectric material 741. A body contact region 795 may beillustrated along the repeating iterations of alternating layers of afirst dielectric material, 730-1, 730-2, . . . , 730-N, a semiconductormaterial, 732-1, 732-2, . . . , 732-N, and a second dielectric material,733-1, 733-2, . . . , 733-N.

FIG. 7F illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 7A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 7F isillustrated, right to left in the plane of the drawing sheet, extendingin the first direction (D1) 709 along an axis of the repeatingiterations of alternating layers of a first dielectric material, 730-1,730-2, . . . , 730-N, a semiconductor material, 732-1, 732-2, . . . ,732-N, and a second dielectric material, 733-1, 733-2, . . . , 733-N,intersecting across the plurality of separate, vertical access lines,740-1, 740-2, . . . , 740-4, and intersecting regions of thesemiconductor material, 732-1, 732-2, . . . , 732-N, in which a channelregion may be formed, separated from the plurality of separate, verticalaccess lines, 740-1, 740-2, . . . , 740-4, by the gate dielectric 738.In FIG. 7E, the first dielectric fill material 739 is shown separatingthe space between neighboring horizontally oriented access devices whichmay be formed extending into and out from the plane of the drawing sheetas described in connection with FIGS. 4A-4K, and can be spaced along afirst direction (D1) 709 and stacked vertically in arrays extending inthe third direction (D3) 711 in the three dimensional (3D) memory.

FIG. 8A illustrates an example method, at a stage of a fabricationprocess for a semiconductor device, such as illustrated in FIGS. 1-3 ,in accordance with a number of embodiments of the present disclosure.FIG. 8A illustrates a top down view of a semiconductor structure, at aparticular point in time, in a fabrication process, according to one ormore embodiments. As illustrated in FIG. 8A, the semiconductor structureincludes an array region 860 and a periphery region 862. As shown inFIG. 8A, a photolithographic process to pattern the photolithographicmasks 835, 836 and/or 837, e.g., 635, 636, and/or 637 in FIGS. 6A-6E or735, 736 , and/or 737 in FIGS. 7A-7F. FIG. 8A illustrates verticalopening 851 in a storage node region 850 through the vertical stackformed by one or more etchant processes. FIG. 8A illustrates a number ofvertical openings 864 in the periphery region 862 formed by one or moreetchant processes. The vertical opening 864 can be similar, e.g. thesame as other than location, to the vertical opening 851 in the arrayregion 860; however, embodiments are not so limited. The one or moreetchant processes forms a vertical opening 851 to expose third sidewallsin the repeating iterations of alternating layers of a first dielectricmaterial, 830-1, 830-2, . . . , 830-N, a semiconductor material, 832-1,832-2, . . . , 832-N, and a second dielectric material, 833-1, 833-2, .. . , 833-N, in the vertical stack, shown in FIGS. 8B-8E, adjacent asecond region of the semiconductor material. Other numerated componentsmay be analogous to those shown and discussed in connection with FIGS. 6and 7 . In some embodiments, this process is performed after selectivelyremoving an access device region of the semiconductor material in whichto form a first source/drain region, channel region, and secondsource/drain region of the horizontally oriented access devices, asillustrated in FIG. 7 .

FIG. 8B illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As illustrated in FIG. 8B andpreviously discussed, a number of vertical openings 864, e.g. verticalopenings for capacitor formation, are formed in the periphery region862. As mentioned, periphery capacitor formation in the periphery region862 can be concurrently performed with array capacitor formation in thearray region, e.g. 860 shown in FIG. 8A.

A bottom electrode material 861 can be deposited, e.g. conformallydeposited, in the number of vertical openings 864. As shown in FIG. 8B,the bottom electrode material 861 is deposited in the horizontalopenings 866. As shown in FIG. 8B, the bottom electrode material 861 maycontact a portion of the semiconductor material 832 located in theperiphery region 862, e.g. located within horizontal opening 866. Thebottom electrode material 861 can be a conductive material, such as ametal. Examples of the bottom electrode material 861 include, but arenot limited to, platinum (Pt) material, a ruthenium (Ru) material, atitanium nitride (TiN) material, a doped TiN material, a tungsten (W)material, a molybdenum (Mo) material, a tantalum nitride (TaN) material,an aluminum (Al) material, a rhodium (Rh) material, a tungsten nitride(WN) material, and a ruthenium oxide (RuO₂) material. One or moreembodiments provide that the bottom electrode material 861 is a titaniumnitride (TiN) material. One or more embodiments provide that the bottomelectrode material 861 can be a doped material. The bottom electrodematerial 861 can be deposited to have a thickness, e.g. a distanceperpendicular from a surface the bottom electrode material 861 isdeposited on, equal to or greater than 5 nm.

FIG. 8C illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown in FIG. 8C, portions ofthe bottom electrode material 861 can be removed, e.g., such thatportions of the bottom electrode material 861 deposited in thehorizontal openings 866 are maintained while portions of bottomelectrode material 861 deposited elsewhere are removed. Portions of thebottom electrode material 861 can be removed by an atomic layer etching(ALE) process and/or other suitable techniques.

FIG. 8D illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown in FIG. 8D, a dielectricmaterial 863 can be deposited, e.g. conformally deposited, in the numberof vertical openings 864. As shown in FIG. 8D, the dielectric material863 is deposited in the horizontal openings 866, e.g. on the bottomelectrode material 861. Examples include, but are not limited to, SiO₂,Si₃N₄, ZiO₂(Zr oxide), HfO₂(Hf oxide), La₂O₃(La oxide), PZT (LeadZirconate Titanate, Pb[Zr(x)Ti(1−x)]O3), BaTiO₃, Al₂O₃ and combinationsthereof. One or more embodiments provide that the dielectric material863 can be doped. The dielectric material 863 can be deposited to have athickness, e.g. a distance perpendicular from a surface the dielectricmaterial 863 is deposited on, from 2 to 10 nm, for example.

FIG. 8E illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown in FIG. 8E, a topelectrode material 856 can be deposited in the number of verticalopenings 864. As shown in FIG. 8E, the top electrode material 856 isdeposited in the horizontal openings 866, e.g. on the dielectricmaterial 863. Depositing the top electrode material 856 forms acapacitor 884, i.e. a metal-insulator-metal capacitor, in each of thehorizontal openings 866, where the top electrode material 856 is acommon electrode material for each of the respective capacitors 884. Thetop electrode material 856 can be a conductive material, such as ametal. Examples of the top electrode material 856 include, but are notlimited to, platinum (Pt) material, a ruthenium (Ru) material, atitanium nitride (TiN) material, a doped TiN material, a tungsten (W)material, a molybdenum (Mo) material, a tantalum nitride (TaN) material,an aluminum (Al) material, a rhodium (Rh) material, a tungsten nitride(WN) material, and a ruthenium oxide (RuO₂) material. One or moreembodiments provide that the top electrode material 856 is a titaniumnitride (TiN) material. One or more embodiments provide that the topelectrode material 856 can be doped, such as doped Si, doped Ge, ordoped SiGe, such as boron doped SiGe, for example. One or moreembodiments provide, while not illustrated that an additional metalmaterial may be formed on the top electrode material 856, e.g., to helpreduce resistance. Examples of the additional metal material include,but are not limited to, W, Ti, TiN, Co, Mo, Ru, silicides of thesemetals and combinations thereof.

FIG. 8F illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown in FIG. 8F, a number ofvertical openings 868, e.g. vertical openings for a bottom electrodecontact material to be deposited, are formed in the periphery region862. The vertical openings 868 can be similar, e.g. the same as otherthan location, to the vertical openings 851 in the array region 860;however, embodiments are not so limited. The vertical openings 868 canbe similar to the vertical openings 864 in the periphery region 862;however, embodiments are not so limited. While FIG. 8F illustrates thatthe vertical openings 868 are formed subsequently to forming thevertical openings 864, e.g. after forming the capacitors 884 in theperiphery region 862, embodiments are not so limited. For instance, thevertical openings 868 can be formed and the bottom electrode contactmaterial, as discussed further herein, may be deposited prior to formingthe vertical openings 864 for capacitor formation and thereafter thecapacitors 884 may be formed. In other words, process steps illustratedin FIGS. 8F-8H can be performed prior to capacitor formation asdiscussed in regard to FIGS. 7C-7D and/or FIGS. 8B-8E, for instance.

FIG. 8G illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown in FIG. 8G, a portion ofthe semiconductor material 832 located in the periphery region 862 canbe selectively removed to form horizontal openings 882. The horizontalopenings 882 can be formed such that the bottom electrode material 861is exposed, e.g. each respective bottom electrode material 861 can beaccessed through a respective horizontal opening 882. It is noted thatwhen the bottom electrode contact material 880, as discussed furtherherein, is deposited prior to capacitor 884 formation, the horizontalopenings 866 can be formed such that the bottom electrode contactmaterial is exposed, e.g. such that the bottom electrode material 861can be deposited thereon.

FIG. 8H illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown in FIG. 8H, a bottomelectrode contact material 880 can be deposited in the horizontalopenings 882 and the vertical openings 868. As shown in FIG. 8H, abottom electrode contact material 880 can be formed on, e.g. in contactwith, each of the respective bottom electrode materials 861. Forming thebottom electrode contact material 880 on the respective bottom electrodematerials 861 can provide that the bottom electrode contact material 880is electrically coupled, e.g. commonly coupled, to the bottom electrodematerials 861 of the respective capacitors. The bottom electrode contactmaterial 880 can be a conductive material, such as a metal. Examples ofthe bottom electrode contact material 880 include, but are not limnedto, platinum (Pt) material, a ruthenium (Ru) material, a titaniumnitride (TiN) material, a doped TiN material, a tungsten (W) material, amolybdenum (Mo) material, a tantalum nitride (TaN) material, an aluminum(Al) material, a rhodium (Rh) material, a tungsten nitride (WN)material, and a ruthenium oxide (RuO₂) material. One or more embodimentsprovide that the bottom electrode contact material 880 is a titaniumnitride (TiN) material. One or more embodiments provide that the bottomelectrode contact material 880 can be a doped material.

FIG. 8I illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown schematically in FIG. 8I,a number of electrical contacts 881-1, 881-2, and 883 can be formed toprovide desired capacitance values. The contacts can be formed as partof BEOL processing, for example. As shown in FIG. 8I, contact 881-1 iscoupled to a first group of capacitors commonly coupled (in parallel) toa bottom electrode contact 880. Contact 883 is coupled to the common topelectrode contact 856. Contact 881-2 is coupled to a second group ofcapacitors commonly coupled (in parallel) to a different bottomelectrode contact 880. The first and second groups of capacitors can beconnected in parallel to provide an increased capacitance, which isdesirable for a number of applications. Since the periphery regionincludes multiple instances of vertically stacked capacitors formed inaccordance with embodiments described herein, the various capacitorgroups can be electrically coupled in various manners, e.g., serially orin parallel, to achieve various desired capacitance values.

FIG. 8J illustrates a section of the periphery region 862 at aparticular point in one example of a fabrication process of anembodiment of the present disclosure. As shown schematically in FIG. 8J,a number of electrical contacts 881-1 and 881-2 can be formed to providedesired capacitance values. The contacts can be formed as part of BEOLprocessing, for example. As shown in FIG. 8J, contact 881-1 is coupledto a first group of capacitors commonly coupled (in parallel) to abottom electrode contact 880. Contact 881-2 is coupled to a second groupof capacitors commonly coupled (in parallel) to a different bottomelectrode contact 880. The first group and the second group can beconnected in series to provide decreased electric field across thecapacitors, which is desirable for a number of applications. Since theperiphery region includes multiple instances of vertically stackedcapacitors formed in accordance with embodiments described herein, thevarious capacitor groups can be electrically coupled in various manners,e.g., serially or in parallel, to achieve various desired capacitancevalues.

FIG. 8K illustrates a cross sectional view, taken along cut-line A-A′ inFIG. 8A, showing another view of the semiconductor structure at thisparticular point in one example a fabrication process of an embodimentof the present disclosure. The cross sectional view shown in FIG. 8K isaway from the plurality of separate, vertical access lines, 840-1,840-2, . . . , 840-N, 840-(N+1), . . . , 840-(Z−1), and shows repeatingiterations of alternating layers of a dielectric material, 830-1, 830-2,. . . , 830-(N+1), separated by horizontally oriented capacitor cellshaving first electrodes 861, e.g., bottom cell contact electrodes, celldielectrics 863, and second electrodes 856, e.g., top, common nodeelectrodes, on a semiconductor substrate 800 to form the vertical stack.As shown in FIG. 8B, a vertical direction 811 is illustrated as a thirddirection (D3), e.g., z-direction in an x-y-z coordinate system,analogous to the third direction (D3) 111, among first, second and thirddirections, shown in FIGS. 1-3 . The plane of the drawing sheet,extending right and left, is in a first direction (D1) 809. In theexample embodiment of FIG. 8K, the first electrodes 861, e.g., bottomelectrodes to be coupled to source/drain regions of horizontal accessdevices, and second electrodes 856 are illustrated separated by a celldielectric material 863 extending into and out of the plane of thedrawing sheet in second direction (D2) and along an axis of orientationof the horizontal access devices and horizontal storage nodes of thearrays of vertically stacked memory cells of the three dimensional (3D)memory. According to an example embodiment, e.g., as shown in FIG. 8K,the fabrication comprises selectively etching the second region of thesemiconductor material, 832-1, 832-2, . . . , 832-N, to deposit a secondsource/drain region and capacitor cells through the second horizontalopening, which is a second horizontal distance back from a verticalopening, e.g., 851, in the vertical stack. In some embodiments, themethod comprises forming capacitor cells as the storage nodes in thesecond horizontal opening of the periphery region 860. By way ofexample, and not by way of limitation, forming the capacitor comprisesusing an atomic layer deposition (ALD) process to sequentially deposit,in the second horizontal opening, a first electrode 861 and a secondelectrode 856 separated by a cell dielectric 863. Other suitablefabrication techniques and/or storage nodes structures may be used. Adigit line 877 may be seen along the plurality of separate, verticalaccess lines 840.

FIG. 8L illustrates a cross sectional view, taken along cut-line B-B′ inFIG. 8A, showing another view of the semiconductor structure at thisparticular point in one example of a fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 8L is illustrated extending in the second direction (D2) 805, leftand right along the plane of the drawing sheet, along an axis of therepeating iterations of alternating layers of a first dielectricmaterial, 830-1, 830-2, . . . , 830-N, a semiconductor material, 832-1,832-2, . . . , 832-N, and a second dielectric material, 833-1, 833-2, .. . , 833-N, along and in which the horizontally oriented access devicesand horizontally oriented storage nodes, e.g., capacitor cells, can beformed within the layers of semiconductor material, 832-1, 832-2, . . ., 832-N. In the example embodiment of FIG. 8L, the horizontally orientedstorage nodes, e.g., capacitor cells, are illustrated as having beenformed been formed in this fabrication process and first electrodes 861,e.g., bottom electrodes to be coupled to source/drain regions ofhorizontal access devices, and second electrodes 856, e.g., topelectrodes to be coupled to a common electrode plane such as a groundplane, separated by cell dielectrics 863, are shown. However,embodiments are not limited to this example. In other embodiments thefirst electrodes 861, e.g., bottom electrodes to be coupled tosource/drain regions of horizontal access devices, and second electrodes856, e.g., top electrodes to be coupled to a common electrode plane suchas a ground plane, separated by cell dielectrics 863, may be formedsubsequent to forming a first source/drain region, a channel region, anda second source/drain region in a region of the semiconductor material,832-1, 832-2, . . . , 832-N, intended for location, e.g., placementformation, of the horizontally oriented access devices, described next.

In the example embodiment of FIG. 8L, the horizontally oriented storagenodes having the first electrodes 861, e.g., bottom electrodes to becoupled to source/drain regions of horizontal access devices, and secondelectrodes 856, e.g., top electrodes to be coupled to a common electrodeplane such as a ground plane, are shown formed in a second horizontalopening, e.g., 779 shown in FIG. 7C, extending in second direction (D2),left and right in the plane of the drawing sheet, a second distance (D2opening) from the vertical opening, e.g., 751 in FIG. 7C, formed in thevertical stack, e.g., 401 in FIG. 4A, and along an axis of orientationof the horizontal access devices and horizontal storage nodes of thearrays of vertically stacked memory cells of the three dimensional (3D)memory. In FIG. 8L, a neighboring, opposing vertical access line 840-3is illustrated by a dashed line indicating a location set inward fromthe plane and orientation of the drawing sheet.

Conductive material 877 may be illustrated adjacent second dielectricmaterial 833. The conductive material 877 may remain in directelectrical contact on a top surface of the first source/drain region875. As such, the conductive material 877 remains in electrical contactwith the source/drain region 875. In some embodiments, the thirddielectric material 874 may be below the first dielectric material 830while remaining in direct contact with the conductive material 877, thefirst source/drain region 875, and the first portion of the low dopedsemiconductor material 832. The third dielectric material 874 may form adirect, electrical contact with a high doped, p-type (p+) siliconmaterial 895, e.g., the body region contact of the horizontally orientedaccess device.

FIG. 8M illustrates a cross sectional view, taken along cut-line C-C′ inFIG. 8A, showing another view of the semiconductor structure at thisparticular point in one example of a fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 8M is illustrated extending in the second direction (D2) 805, leftand right in the plane of the drawing sheet, along an axis of therepeating iterations of alternating layers of a first dielectricmaterial, 830-1, 830-2, . . . , 830-N, a semiconductor material, 832-1,832-2, . . . , 832-N, and a second dielectric material, 833-1, 833-2, .. . , 833-N, outside of a region in which the horizontally orientedaccess devices and horizontally oriented storage nodes, e.g., capacitorcells, will be formed within the layers of semiconductor material,832-1, 832-2, . . . , 832-N. In FIG. 8L, the dielectric material 841 isshown filling the space between the horizontally oriented accessdevices, which can be spaced along a first direction (D1), extendinginto and out from the plane of the drawings sheet, for a threedimensional array of vertically oriented memory cells. However, in thecross sectional view of FIG. 8M, the second electrode 856, e.g., top,common electrode to a capacitor cell structure, is additionally shownpresent in the space between horizontally neighboring devices. At theleft end of the drawing sheet is shown the repeating iterations ofalternating layers of a first dielectric material, 830-1, 830-2, . . . ,830-N, a semiconductor material, 832-1, 832-2, . . . , 832-N, and asecond dielectric material, 833-1, 833-2, . . . , 833-N, at whichlocation a horizontally oriented digit line, e.g., digit lines 107-1,107-2, . . . , 107-P shown in FIG. 1 , et. seq., can be integrated toform electrical contact with the second source/drain regions or digitline conductive contact material, described in more detail below.

In some embodiments, a conductive material 877 may be illustratedadjacent second dielectric material 833. The conductive material 877 maybe adjacent dielectric material 841. A body contact region 895 may alsobe illustrated along the repeating iterations of alternating layers of afirst dielectric material, 830-1, 830-2, . . . , 830-N, a semiconductormaterial, 832-1, 832-2, . . . , 832-N, and a second dielectric material,833-1, 833-2, . . . , 833-N.

FIG. 8N illustrates a cross sectional view, taken along cut-line D-D′ inFIG. 8A, showing another view of the semiconductor structure at thisparticular point in one example of a fabrication process of anembodiment of the present disclosure. The cross sectional view shown inFIG. 8N is illustrated, right to left in the plane of the drawing sheet,extending in the first direction (D1) 809 along an axis of the repeatingiterations of alternating layers of a first dielectric material, 830-1,830-2, . . . , 830-N, a semiconductor material, 832-1, 832-2, . . . ,832-N, and a second dielectric material, 833-1, 833-2, . . . , 833-N,intersecting across the plurality of separate, vertical access lines,840-1, 840-2, . . . , 840-4, and intersecting regions of thesemiconductor material, 832-1, 832-2, . . . , 832-N, in which a channelregion may be formed, separated from the plurality of separate, verticalaccess lines, 840-1, 840-2, . . . , 840-4, by the gate dielectric 838.In FIG. 8N, the first dielectric fill material 839 is shown separatingthe space between neighboring horizontally oriented access devices andhorizontally oriented storage nodes, which may be formed extending intoand out from the plane of the drawing sheet as described in more detailbelow, and can be spaced along a first direction (D1) 809 and stackedvertically in arrays extending in the third direction (D3) 811 in thethree dimensional (3D) memory.

FIG. 9 illustrates a cross-sectional view of a portion of an examplehorizontally oriented access device coupled to a horizontally orientedstorage node and coupled to vertically oriented access lines andhorizontally oriented digit lines, as may form part of an array ofvertically stacked memory cells, in accordance with a number ofembodiments of the present disclosure. The horizontally oriented accessdevice 901 can have a first source/drain region and a second sourcedrain region separated by a channel region, and gates opposing thechannel region and separated therefrom by a gate dielectric.

FIG. 9 is a block diagram of an apparatus in the form of a computingsystem 900 including a semiconductor device 990, e.g. a memory device,in accordance with a number of embodiments of the present disclosure. Asused herein, a memory device 990, a memory array 991, and/or a host 992,for example, might also be separately considered an “apparatus.”According to embodiments, the semiconductor device 992 may comprise atleast one memory array 991, including the periphery region 962 asdiscussed herein, with a memory cell formed having a digit line and bodycontact, according to the embodiments described herein.

In this example, system 900 includes a host 992 coupled to memory device990 via an interface 993. The computing system 900 can be a personallaptop computer, a desktop computer, a digital camera, a mobiletelephone, a memory card reader, or an Internet-of-Things (IoT) enableddevice, among various other types of systems. Host 992 can include anumber of processing resources, e.g., one or more processors,microprocessors, or some other type of controlling circuitry, capable ofaccessing memory 990. The system 900 can include separate integratedcircuits, or both the host 992 and the memory device 990 can be on thesame integrated circuit. For example, the host 992 may be a systemcontroller of a memory system comprising multiple memory devices 990,with the system controller 994 providing access to the respective memorydevices 990 by another processing resource such as a central processingunit (CPU).

In the example shown in FIG. 9 , the host 992 is responsible forexecuting an operating system (OS) and/or various applications, e.g.,processes, that can be loaded thereto, e.g., from memory device 1003 viacontroller 1005. The OS and/or various applications can be loaded fromthe memory device 990 by providing access commands from the host 992 tothe memory device 990 to access the data comprising the OS and/or thevarious applications. The host 992 can also access data utilised by theOS and/or various applications by providing access commands to thememory device 990 to retrieve said data utilized in the execution of theOS and/or the various applications.

For clarity, the system 900 has been simplified to focus on featureswith particular relevance to the present disclosure. The memory array991 can be a DRAM array comprising at least one memory cell having adigit line and body contact formed according to the techniques describedherein. For example, the memory array 991 can be an unshielded DL 4F2array such as a 3D-DRAM memory array. The array 991 can comprise memorycells arranged in rows coupled by word lines (which may be referred toherein as access lines or select lines) and columns coupled by digitlines (which may be referred to herein as sense lines or data lines).Although a single array 991 is shown in FIG. 9 , embodiments are not solimited. For instance, memory device 990 may include a number of arrays991, e.g., a number of banks of DRAM cells.

The memory device 990 includes address circuitry 995 to latch addresssignals provided over an interface 993. The interface can include, forexample, a physical interface employing a suitable protocol, e.g., adata bus, an address bus, and a command bus, or a combineddata/address/command bus. Such protocol may be custom or proprietary, orthe interface 993 may employ a standardized protocol, such as PeripheralComponent Interconnect Express (PCIe), Gen-Z, CCIX, or the like. Addresssignals are received and decoded by a row decoder 996 and a columndecoder 997 to access the memory array 991. Data can be read from memoryarray 991 by sensing voltage and/or current changes on the sense linesusing sensing circuitry 998. The sensing circuitry 998 can comprise, forexample, sense amplifiers that can read and latch a page (e.g., row) ofdata from the memory array 991. The I/O circuitry 999 can be used forbi-directional data communication with the host 992 over the interface993. The read/write circuitry 955 is used to write data to the memoryarray 991 or read data from the memory array 991. As an example, thecircuitry 955 can comprise various drivers, latch circuitry, etc.

Control circuitry 994 decodes signals provided by the host 992. Thesignals can be commands provided by the host 992. These signals caninclude chip enable signals, write enable signals, and address latchsignals that are used to control operations performed on the memoryarray 991, including data read operations, data write operations, anddata erase operations. In various embodiments, the control circuitry 994is responsible for executing instructions from the host 992. The controlcircuitry 994 can comprise a state machine, a sequencer, and/or someother type of control circuitry, which may be implemented in the form ofhardware, firmware, or software, or any combination of the three and maycomprise one or more registers 957. In some examples, the host 992 canbe a controller external to the memory device 990. For example, the host992 can be a memory controller which is coupled to a processing resourceof a computing device.

The term semiconductor can refer to, for example, a material, a wafer,or a substrate, and includes any base semiconductor structure.“Semiconductor” is to be understood as including silicon-on-sapphire(SOS) technology, silicon-on-insulator (SOI) technology,thin-film-transistor (TFT) technology, doped and undoped semiconductors,epitaxial silicon supported by a base semiconductor structure, as wellas other semiconductor structures. Furthermore, when reference is madeto a semiconductor in the preceding description, previous process stepsmay have been utilized to form regions/junctions in the basesemiconductor structure, and the term semiconductor can include theunderlying materials containing such regions/junctions.

As used herein, “a number of” or a “quantity of” something can refer toone or more of such things. For example, a number of or a quantity ofmemory cells can refer to one or more memory cells. A “plurality” ofsomething intends two or more. As used herein, multiple acts beingperformed concurrently refers to acts overlapping, at least in part,over a particular time period. As used herein, the term “coupled” mayinclude electrically coupled, directly coupled, and/or directlyconnected with no intervening elements (e.g., by direct physicalcontact), indirectly coupled and/or connected with intervening elements,or wirelessly coupled. The term coupled may further include two or moreelements that co-operate or interact with each other (e.g., as in acause and effect relationship). An element coupled between two elementscan be between the two elements and coupled to each of the two elements.

It should be recognized the term vertical accounts for variations from“exactly” vertical due to routine manufacturing, measuring, and/orassembly variations and that one of ordinary skill in the art would knowwhat is meant by the term “perpendicular.” For example, the vertical cancorrespond to the z-direction. As used herein, when a particular elementis “adjacent to” an other element, the particular element can cover theother element, can be over the other element or lateral to the otherelement and/or can be in direct physical contact the other element.Lateral to may refer to the horizontal direction (e.g., the y-directionor the x-direction) that may be perpendicular to the z-direction, forexample.

Although specific embodiments have been illustrated and describedherein, those of ordinary skill in the art will appreciate that anarrangement calculated to achieve the same results can be substitutedfor the specific embodiments shown. This disclosure is intended to coveradaptations or variations of various embodiments of the presentdisclosure. It is to be understood that the above description has beenmade in an illustrative fashion, and not a restrictive one. Combinationof the above embodiments, and other embodiments not specificallydescribed herein will be apparent to those of skill in the art uponreviewing the above description. The scope of the various embodiments ofthe present disclosure includes other applications in which the abovestructures and methods are used. Therefore, the scope of variousembodiments of the present disclosure should be determined withreference to the appended claims, along with the full range ofequivalents to which such claims are entitled.

What is claimed is:
 1. A three-dimensional memory device, comprising: anarray of vertically stacked memory cells, the array of verticallystacked memory cells, comprising: horizontally oriented access deviceseach having a first source/drain region and a second source drain regionseparated by a channel region, and gates opposing the channel region andseparated therefrom by a gate dielectric; access lines coupled to thegates and separated from the channel region by the gate dielectric;horizontally oriented storage nodes, in an array region, electricallycoupled to the second source/drain regions of the horizontally orientedaccess devices, wherein the horizontally oriented storage nodes arearray region capacitors; digit lines electrically coupled to the firstsource/drain regions of the horizontally oriented access devices;horizontally oriented periphery region vertically stacked capacitors, ina periphery region, wherein each of the horizontally oriented peripheryregion vertically stacked capacitors includes a bottom electrodematerial, a dielectric material, and a top electrode material; and abottom electrode contact material formed in the periphery region,wherein the bottom electrode contact material is electrically coupled tothe bottom electrode materials of the horizontally oriented peripheryregion vertically stacked capacitors, in the periphery region, andwherein the bottom electrode contact material is coupled to anelectrical contact that is formed as part of back end of lineprocessing.
 2. The three-dimensional memory device of claim 1, whereinthe top electrode material is a common top electrode material.
 3. Thethree-dimensional memory device of claim 1, wherein the access lines arevertically oriented access lines and the digit lines are horizontallyoriented digit lines.
 4. A three-dimensional memory device, comprising:an array of vertically stacked memory cells comprising array regioncapacitors, wherein the array region capacitors are storage nodes; and aperiphery region comprising: a plurality of periphery region verticallystacked capacitors formed in the periphery region, wherein each of theplurality of periphery region capacitors has a respective bottomelectrode material and the plurality of periphery region capacitors havea common top electrode material, wherein the respective bottom electrodematerial and the common top electrode material are separated by adielectric material; and a bottom electrode contact material formed inthe periphery region, wherein the bottom electrode contact material iselectrically coupled to each of the respective bottom electrodematerials, wherein the plurality of periphery region capacitors formedin the periphery region are coupled to an electrical contact that isformed as part of back end of line processing and the plurality ofperiphery region capacitors formed in the periphery region are notdirectly coupled to a respective digit line or respective access line ofthe array of vertically stacked memory cells.
 5. The three-dimensionalmemory device of claim 4, wherein the bottom electrode contact materialis formed on a channel material.
 6. The three-dimensional memory deviceof claim 4, wherein the plurality of periphery region capacitors arehorizontally oriented capacitors.
 7. The three-dimensional memory deviceof claim 4, wherein the bottom electrode material is a first metal, thecommon top electrode material is a second metal, the bottom electrodecontact material is a third metal, and the third metal is different thanthe first metal.